2020

 

2019

Adaptive Adversarial Videos on Roadside Billboards: Dynamically Modifying Trajectories of Autonomous Vehicles
N. Patel, P. Krishnamurthy, S. Garg, and F. Khorrami
IROS'19

CompAct: On-chip Compression of Activations for Low PowerSystolic Array Based CNN Acceleration
J. Zhang, P. Raj, S. Zarar, A. Ambardekar, S. Garg 
IEEE Transactions on Embedded Computing Sytems (Special Issue on Papers from ESWeek 2019)

Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators
J. Zhang, Z Ghodsi, K Rangineni, S. Garg
IEEE Design and Test of Computers

A Concentration of Measure Approach to Database De-anonymization
F. Shirani, S. Garg, E. Erkip
IEEE Symposium on Information Theory (ISIT)

Don’t Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication
M.I. Mera, S. Garg
IEEE Embedded Systems Letters

The SAT Attack on IC Camouflaging: Impact and Potential Countermeasures
M. El-Massad, S. Garg, M. Tripunitara
IEEE Transactions on Computer-Aided Design of Electronic Systems (Special Issue on Top Picks in Hardware and Embedded Systems Security)

Fault-tolerant Systolic Array Based Accelerators for Deep Neural Network Execution
J. Zhang, K. Basu, S. Garg
IEEE Design and Test of Computers

BadNets: Evaluating Backdooring Attacks on Deep Neural Networks
Tianyu Gu, Kang Liu, Brendan Dolan-Gavitt, Siddharth Garg
IEEE Access

Split Manufacturing Based Register Transfer Level Obfuscation
Xiaotong Cui, Jeff (Jun) Zhang, Kaijie Wu, Siddharth Garg, Ramesh Karri
ACM Journal on Emerging Technologies in Computing

TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint
I.F. Abbassi, F. Khalid, S. Rehman, A. Kamboh, A. Jantsch, S. Garg, M. Shafique
DATE 2019

2018

TaintHLS A HighLevel Synthesis Approach to Dynamic Information Flow Tracking in Hardware Accelerators
C. Pilato, S. Garg, R. Karri, F. Regazzoni
IEEE Transactions on Computer-Aided Design

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis. 
Christian Pilato, Siddharth Garg, Kaijie Wu, Ramesh Karri, Francesco Regazzoni
IEEE Embedded Systems Letters

FATE: fast and accurate timing error prediction framework for low power DNN accelerator design
J. Zhang, S. Garg
ICCAD'18

Fine-Pruning: Defending Against Backdooring Attacks on Deep Neural Networks
K. Liu, B. Dolan-Gavitt, S. Garg
RAID'18

Optimal Active Social Network De-anonymization Using Information Thresholds
F. Shirani, S. Garg, E. Erkip
ISIT'18

Typicality Matching for Pairs of Correlated Graphs
F. Shirani, S. Garg, E. Erkip
ISIT'18

ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators
J. Zhang, Z. Ghodsi, S. Garg.
DAC'18

TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis
C. Pilato, F. Ragazzoni, R. Karri, S. Garg
DAC'18

Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
J. Zhang, T. Gu, B.D. Gavitt, S. Garg.
VTS'18 [Best Paper Award Nomination]

2017

Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications.
Y. Turakhia, G. Liu, S. Garg, D. Marculescu.
IEEE Transactions on Computers 

Computing in the Dark Silicon Era: Current Trends and Research Challenges
M. Shafique, S. Garg
IEEE Design & Test of Computers

SafetyNets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud
Z. Ghodsi, T. Gu, S. Garg.
NIPS'17

BadNets: Identifying Vulnerabilities in the Machine Learning Model Supply Chain 
T. Gu, B.D. Gavitt, S. Garg.
NIPS MLSec Workshop'17 [Best Attack Paper!]

Reverse Engineering Camouflaged Sequential Circuits Without Scan Access
M. El-Massad, S. Garg, M. Tripunitara.
ICCAD'17

Optimal Checkpointing for Secure Intermittently Powered IoT Devices.
Z. Ghodsi, S. Garg, R. Karri.
ICCAD'17

Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques
A. Sengupta, S. Patnaik, J. Knechtel, M. Ashraf, S. Garg and O. Sinanoglu.
ICCAD'17

An Information Theoretic Framework for Active De-Anonymization in Social Networks Based on Group Memberships.
F. Shirani, S. Garg, E. Erkip.
Allerton'17

IoT-enabled Distributed Cyber-attacks on Transmission and Distribution Grids.
Y. Dvorkin, S. Garg.
NAPS'17

The Need for Declarative Properties in Digital IC Security.
M. El Massad, F. Imeson, S. Garg, M. Tripunitara.
GLSVSLI'17

BandiTS: Dynamic timing speculation using multi-armed bandit based optimization.
J. Zhang, S. Garg.
DATE'17

2016

Fragility of the Commons under Prospect-Theoretic Risk Attitudes.
A. Hota, S. Garg, S. Sundaram.
Games and Economic Behavior

Variability- and Reliability-Awareness in the Age of Dark Silicon.
F. Kriebel, S. Rehman, M. Shafique, S. Garg and J. Henkel.
IEEE Design and Test of Computers

Optimal De-Anonymization in Random Graphs with Community Structure.
E. Onoran, S. Garg and E. Erkip.
Asilomar'16

Non-Deterministic Timers for Hardware Trojan Activation (Or How a Little Randomness Can Go the Wrong Way)
F Imeson, S Nejati, S Garg and M Tripunitara.
USENIX WOOT'16

Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks.
M.I. Mera, M. El-Massad, S. Garg.
ISVLSI'16

Synergistic Timing Speculation for Multi-threaded Programs.
A. Yasin, J. Zhang, H. Chen, S. Chakraborty, S. Garg, K. Chakraborty.
DAC'16

Verifiable ASICs.
R.S. Wahby, M. Howard. S. Garg, a. shelat, M. Walfish.
Oakland S&P'16 [Distinguished Student Paper Award!]

2015

Energy Storage and Regulation: An Analysis.
D. Fooladivanda, C. Rosenberg, S. Garg.
IEEE Trans. Smart Grid. 

Learning-Based Power/Performance Optimization for Many-Core Systems with Extended-Range Voltage/Frequency Scaling.
E. Cai, D.-C. Juang, S. Garg, J. Park and D. Marculescu.
IEEE Transactions on Computer-Aided Design 

Analysis of Energy- And SoC-Neutral Contracts for Frequency Regulation with Energy Storage
D. Fooladivanda, C. Rosenberg, and S. Garg,
SmartGridComm'15

Energy Efficient Scheduling for Web Search on Heterogeneous Micro-Servers
S. Jain, H. Navale, U. Ogras and S. Garg,
ISLPED'15 

Variability-Aware Dark Silicon Management in On-Chip Many-Core Systems
M. Shafique, D. Gnad, S. Garg, J. Henkel,
DATE'15 

IC Decamouflaging: Reverse Engineering Camouflaged ICs Within Minutes
M. El-Massad, S. Garg and M. Tripunitara,
NDSS'15

2014

Reliable Computing with Ultra-Reduced Instruction Set Coprocessors.
Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren D. Patel, Mahesh V. Tripunitara, and Siddharth Garg.
IEEE Micro 

Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors.
Da-Cheng Juan, Siddharth Garg and Diana Marculescu.
ACM TODAES 

An Analysis of Energy Storage and Regulation
D. Fooladivanda C. Rosenberg and S. Garg.
SmartGridComm'14

Job Arrival Rate Aware Scheduling for Asymmetric Multi-core Servers In the Dark Silicon Era
B. Raghunathan and S. Garg.
CODES+ISSS'14

EDA Challenges in the Dark Silicon Era
M. Shafique, S. Garg, J. Henkel and D. Marculescu.
DAC'14 

2013

A Hybrid Amplitude/Time Encoding Scheme for Enhancing Coding Efficiency and Dynamic Range in Digitally Modulated Power Amplifiers.
Jingjing Xia, Siddharth Garg, Slim Boumaiza.
IEEE JETCAS

Addressing Process Variations at the Microarchitecture and System Level.
Siddharth Garg, Diana Marculescu.
Foundations and Trends in Electronic Design Automation.

Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits.
Siddharth Garg, Diana Marculescu.
IEEE TVLSI 

Resource Sharing Games with Failures and Heterogeneous Risk Attitudes
A. Hota, S. Garg and S. Sundaram.
Allerton'13 

Learning the Optimal Operating Point for Many-Core Systems with Extended Range Voltage/Frequency Scaling
D.-C. Juan, S. Garg, J. Park and D. Marculescu.
CODES+ISSS'13

Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation
F. Imeson, A. Emtenan, S. Garg, M. Tripunitara.
USENIX Security'13

HaDeS: Architectural Synthesis for Heterogeneous Dark Silicon Chip Multiprocessors
Y. Turakhia, B. Raghunathan, S. Garg, D. Marculescu.
DAC'13

Impact of Manufacturing Process Variations on Performance and Thermal Characteristics of 3D ICs: Emerging Challenges and New Solutions
D.-C. Juan, S. Garg and D. Marculescu.
ISCAS  (Invited Paper)

Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors
B. Raghunathan, Y. Turakhia, S. Garg, D. Marculescu.
DATE'13 

Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors
S. Ananthanarayanan, S. Garg, H.D. Patel.
DATE'13

Vertically-Addressed Test Structures (VATS) for 3D IC Variability and Stress Measurements
C. O'Sullivan, P. Levine and S. Garg.
ISQED'13

2012

Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip.
Siddharth Garg, Diana Marculescu, Radu Marculescu. ACM Journal on Emerging Technologies IEEE JETC

On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks. 
Siddharth Garg, Diana Marculescu
IEEE TECS

Exploiting Process Variability in Voltage/Frequency Control.
Sebastian Herbert, Siddharth Garg, Diana Marculescu. In IEEE Transactions on VLSI Systems IEEE TVLSI

System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands.
Siddharth Garg, Diana Marculescu.
IEEE TVLSI

EmPower: FPGA Based Rapid Prototyping of Dynamic Power Management Algorithms for Multi-Processor Systems on Chip
C. Ravishankar, S. Ananthanarayanan, S. Garg, A. Kennings,
FPL'12

Reliable Computing with Ultra-Reduced Instruction Set Co-processors
A. Rajendiran, S. Ananthanarayanan, H.D. Patel, M.V. Tripunitara, S. Garg, IEEE/ACM Design DAC'12 

Analysis and Evaluation of Greedy Thread Swapping Based Dynamic Power Management for MPSoC Platforms
C. Ravishankar, S. Ananthanarayanan, S. Garg, A. Kennings,
ISQED'12

2011

Robust Heterogeneous Datacenter Design: A Formal Approach
S. Garg, S. Sundaram and H.D. Patel.
SIGMETRICS PER

Parametric Yield and Reliability of 3D Integrated Circuits: New Challenges and Solutions
S. Garg and D. Marculescu
VTS'11

Statistical Thermal Evaluation and Mitigation Techniques for 3D Chip-Multiprocessors In the Presence of Process Variations
D.-C. Juan, S. Garg, and D. Marculescu
DATE'11

Prior to 2010

S. Garg, D. Marculescu, and S. Herbert, “Process Variation Aware Performance Modeling and Dynamic Power Management for Multicore Systems,” in IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2010. (Embedded tutorial)

S. Garg, D. Marculescu, R. Marculescu, “Custom Feedback Control: Enabling Truly Scalable On-Chip Power Management for MPSoCs,” in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design, Austin, TX, Aug. 2010.

S. Garg, R. Yan, R. Marculescu, D. Marculescu, U. Schlichtmann, “Architectural Modeling of the Impact of Process Variations on Network-on-Chip Clock Frequency,” in Proc. Workshop on Diagnostic Services in Network-on-Chips (DSNOC), in conjunction with ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 2010.

S. Garg, D. Marculescu, R. Marculescu and U. Ogras, “Technology-driven Limits on DVFS Controllability of Multiple Voltage-Frequency Island Designs” in Proc. of IEEE/ACM Design Automation Conference (DAC), Jul. 2009. Best Paper in Session Award

S. Garg and D. Marculescu, “Process Variability Analysis and Mitigation for 3D MPSoCs” in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), Apr. 2009. Best Paper Award Nomination

S. Garg and D. Marculescu, “3D GCP - An Analytical Model for the Impact of Process Variations on the Critical Path Delay of 3D ICs” in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2009. Best Paper Award

S. Garg, D. Marculescu, “System-Level Mitigation of WID Leakage Variations using Body-Bias Islands,” in Proc. ACM/IEEE Intl. Conference on Hardware-Software Codesign and Systems Synthesis (CODES+ISSS), Atlanta, GA, October 2008.

S. Garg, D. Marculescu, “On the Impact of Manufacturing Process Variations On the Lifetime of Sensor Networks,” in Proc. ACM/IEEE Intl. Conference on Hardware-Software Codesign and System Synthesis (CODES-ISSS), Salzburg, Austria, Sept. 2007

S. Garg, D. Marculescu,"System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs,” in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE), Nice, France, Apr. 2007.

D. Marculescu, S. Garg, “System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems,” in Proc. IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2006.

S. Herbert, S. Garg, D. Marculescu, “Reclaiming Performance and Energy Efficiency from Variability,” in 4th Annual Thomas J. Watson P=ac2 Conference (PAC2), Yorktown, NY, Oct. 2006.

Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques