Part I - Summary of the Project

As the data transmission rate increases from today's 10 Gbit/s (OC-192) to 40 Gbit/s (OC-768) or even higher, the duration of the shortest IP packet (40 bytes) is reduced from 32 ns to 8 ns, or even smaller. It will, in turn, cause the bottleneck of resolving the contention among input packets destined for the same output port, and thus limit the switch size and the switch capacity.

Based on the concept of the path switching, we propose a multi-terabit/s multicast ATM switch architecture that interconnects electronic switch modules with a quasi-static controlled optical interconnection network (OIN). Routing in the OIN is predetermined to avoid slot-by-slot processing and to provide flexible switching capacity on virtual path level. The surrounding electronic switch modules support multicasting, fast dynamic routing, and statistical multiplexing to compensate the quasi-static routing in the OIN to achieve totally a multi-terabit/s switching capacity. This quasi-static switching architecture simplifies the design of a multi-terabit/s ATM switch to specially featured 10 Gbit/s switch modules: the electronic multicast input and output modules and optical central interconnection, which are all feasible with existing technology.

We will investigate several approaches of performing output contention resolution within multicast electronic switch modules: determine a cost-effective design for each approach, study the performance in terms of throughput, cell delay and loss rate, and finally identify the best approach that has high performance and feasible construction complexity.

Part II - Technical Information Project Report  

The project report can be found here.
 

Part III - Personnel Ever Supported:

• Faculty
  • Professor H. Jonathan Chao - Overall Project
• Post Doctorate Student(s)
  • Dr. Roberto Rojas-Cessa - VLSI Design
  • Dr. Zhigang Jing - Performance Study
• Graduate Student(s)
  • Guansong Zhang (Ph.D. student) - VLSI Design

Part IV- Publications

"An Optical Interconnection Network for Terabit IP Routers"
H. J. Chao and T. S. Wang
IEEE Journal of Lightwave Technology, vol. 18, no. 12, pp. 2095-2112, Dec. 2000.

"A photonic front-end processor in a WDM ATM multicast switch"
H. J. Chao, et. al
IEEE Journal of Lightwave Technology, Vol. 18, No. 3, pp. 273-285, March 2000.

"All-optical packet routing - architecture and implementation"
F. S. Choa and H. J. Chao
Journal of Photonic Network Communications, Vol. 1, No. 4, pp. 303-311, 1999.

"Design of an Optical Interconnection Network for Terabit IP Router"
H. J. Chao and T. S. Wang
to appear in IEEE LEOS, Orlando, Dec. 1998.

"A photonic ATM front-end processor"
H. J. Chao, et. al
to appear in IEEE LEOS, Orlando, Dec. 1998

"A Fast Arbitration Scheme for Terabit Packet Switches"
H. J. Chao, X. Guo, and C. H. Lam
in IEEE GLOBECOM'99, Brazil, Dec.1999

"A photonic ATM front-end processor"
Y. Fan, L. M. Wang, Y. Chai, F. S. Choa, H. J. Chao, Z. Zhang, L. Wu, and S. Yang
in ECOC'98, Sep. 1998.
 

Part V - Significant Educational Impact from the Project

The research results have been included in the PI's book, Broadband Packet Switching Technologies - A Practical Guide to ATM Switches and IP Routers, published by John Wiley & Sons, Inc, in Sep. 2001. This book is being used in the class EL737 Broadband Packet Switching Sytems, in Polytechnic University.