Part I - Summary of the Project

The objective of this research work is to build a photonic ATM front end processor including the functions of cell delineation, virtual channel identifier (VCI) over-writing, and cell synchronization and for future photonic ATM/IP switches.

Optical networking technology has well progressed in the past few years. The wavelengthdivision- multiplexing (WDM) technology prevails all over the world due to the advantages of bringing a huge capacity to existing optical networks without installing new fibers. Recent development on photonic add/drop multiplexers and reconfigurable photonic switches can further facilitate the optical networking. Compared with using electronic switches, they can handle the traffics in a network more conveniently and cost effectively. All optical networking concept is now well accepted by all carriers including even the most conservative carriers like MCI-Worldcom. Recently, due to the growth of internet, the research topics has further moved toward trying to remove the SONET layer out of the optical networks and allowing IP traffics to directly run on top of WDM channels. To do that, one of the most comprehensive solutions is to run packets directly on top photonic packet switches as proposed by European carriers like BT and Alcatel. In facts, the photonic packet/cell switch research has recently become a very important research area. Our work represents one of the few leading research works in the world in this area.

The moment we proposed the work (1993), we have to take care the need of both an OTDM and a WDM networks. The technologies we developed here are useful for either approach. Basically, for each incoming packet/cell from all the optical channels, we need to align them in time before they entering the NxN space switch fabrics. A tunable optical delay line controlled by calculated electrical signals is needed. We may also need to change the information in the packet header before it leaves the switch and goes to the next node. The information could be the VCI in a system using the virtual-channel routing scheme or the packet delay in a burst switching system where the header is ahead of the packet payload. The delay between the header and the payload is changing at each node due to the add-on packet processing delay and the contention resolution delay. Before achieving both of the above functions (tunable delays and header information overwriting) an important function has to be performed and that is the cell or packet delineation function. The work is basically to identify the packet or cell boundaries from a stream of 1-0 optical signals. In a SONET system, the framing function is provided. When we run IP or cells directly on top of an optical channel, the cell or packet boundaries have to be identified.

Currently, there is basically no practical all optical logic devices. It is not hard to understand that electronic logic and control circuits has to be employed in this project to perform some critical operations. In our proposed switch, optical transparency is maintained everywhere to keep obtaining the advantages of the bandwidth and bit-rate as well as format independence. On the other hand, the intelligence is provided by the electronics. Since many of the functions at 2.5 Gb/s and above are not commercially available, we have to build them ourselves for the system demonstration. In this work, we have built 3 control circuit boards running at 2.5 Gb/s. These include a cell delineation circuit board, a VCI over-writing circuit board, and a cell synchronizer control circuit board. We also design and fabricate an 1x2 semiconductor optical amplifier (SOA) broadband space switch. Multiwavelength-signal switching using the fabricated switches is demonstrated. We also build the VCI overwriting and cell synchronization optical systems using both LiNbO3 switches and the fabricated switches. We have completed the interfaces of the optical systems with the control circuit boards and finally demonstrated the proposed photonic ATM frontend processor at 2.5 Gb/s.

In the project, UMBC is responsible for the optical systems and Polytechnic University (Poly) is responsible for the electronic control systems. There has been many e-mails, phone calls, visits between the two campuses. Since Poly has only a 1 Gb/s testing system and UMBC has a 5Gb/s BER system, many testing works has to be first tuned to 1Gb/s at Poly and moved down to UMBC to be further tuned to 2.5 Gb/s before performing control functions. Poly researchers usually have to stay longer at UMBC to complete the interface and demonstration. The interaction among graduate students has created a great environment that neither campus can singly provide. Many exciting moments, ideas, problem solving discussions, and conference as well as journal papers have been generated through this process.

In the course of the research works, UMBC has graduated two M.S. students and two Ph. D. students (working at Bellcore, Cadence, E-Tek, and a cable TV equipment company at California) and Poly has two Ph. D. students just going to graduate. We have published 6 papers and filed 1 patent. More papers are in the process of preparation. Our works have drawn a great attention from many different equipment vendors and research organizations including NTT optical networking group, Alcatel, CSELT, New Bridge networks, àetc.. The PI, Prof. Choa, was also visited by Cisco and invited by 3-Com to visit their head quarter and give an invited talk on our photonic packet switching research. In facts, a consensus has been reached by the optical communication community that fast photonic circuit switches and photonic packet switches will be the direction for the next generation optical network research.

A basic concept has formed after this research work. In an all-optical network cloud, photonic packet switches will be sitting everywhere in the middle of the cloud as backbone switches. Electronic buffered switches will be sitting on the edge of the cloud as edge switches to do format conversions and traffic regulation. Bursty traffics will be mostly buffered at the edge of the all-optical network and packets go to the same network address will be packed to a large cell with a fixed length before send into the all-optical network. Inside the all-optical network, the backbone switches will handle fixed size cells all optically with fiber delay lines or loop memories. Since the traffics is relatively regulated, the buffer size requirement is more relaxed. Such a concept is now starting to be accepted by many industrial researchers. As a leading research work in the world, our results can greatly contribute to the optical networking area and have impacts to the next generation Internet (NGI) and the global information infrastructure (GII).

We summarize our special achievement in the following: 1. Cell delineation at 2.5 Gb/s. Currently, one of the best ideas to achieve IP on WDM may take the exactly same approach to delineate the IP packet boundary when the SONET framing is not available. We have achieved what many vendors just going to propose.
2. All optical cell header information exchange at 2.5 Gb/s. It is a very important function for future optical burst/packet switches.
3. All optical cell synchronization down to 100 ps resolution. Another very important function for future optical burst/packet switches.

Part II - Technical Information

Project Report, 1998. [pdf file]

Project Report, 2001. [pdf file]