Most Network-on-Chip (NoC) designs for Chip Multiprocessors (CMP) proposed to date use buffered electronic interconnections with planar topologies, such as 2D Mesh and 2D Torus, for ease of implementation. As more tiles and network nodes are put on the same chip, such topologies result in increased latency in delivering packets from one node to another due to additional network hops. The increased number of network hops further cause significant power dissipation, as more memory read/write operations are performed when packets traverse multiple routers. 

The emerging three-dimensional integrated circuit (3D IC) technology provides an attractive solution to addressing the scaling issue. It stacks 2D dies together and connects them in a third dimension. We apply this technology to design on-chip interconnection networks for 3D CMP with maximum power and latency/throughput performance. In this project, we are exploiting state-of-the-art silicon photonics with 3D IC technologies to design a large-scale, high-performance, and power-effective bufferless Clos network-on-chip for 3D CMPs. Such a bufferless approach reduces the number of buffer writes/reads, leading to less power dissipation and queueing delay on the forwarding path.

Some photonic components that are used in the design of a photonic Clos NOC are explained below. 

(1) Point-to-point Photonic Link
Figure 3 shows a point-to-point photonic link. An off-chip laser source injects ? different wavelengths of light into the power waveguide. The sender, which has a set of modulation rings (denoted with "M", each corresponding to a wavelength) in between the power waveguide and the data waveguide, activates the modulation rings, and redirects the light with the corresponding wavelengths into the data waveguide. Different wavelengths of light travel through the data waveguide until they drop into the filter rings (denoted with "F" in the figure), which are activated by the receiver. In this project, ? is always assumed to be 64, which is the size of a flit. All 64 wavelengths are bundled together, and are transmitted/received simultaneously.

Fig. 3. Point-to-point photonic link.
 

(2) N-to-1 MUX Waveguide and NxN Photonic XBar

The N-to-1 MUX waveguide is very similar to the point-to-point photonic link. The difference is that there are multiple senders in a MUX waveguide (as shown in Figure 4). In an N-to-1 MUX waveguide, there are N senders and one receiver attached to the data waveguide. At any given time, only one sender is allowed to modulate the light and send data to the receiver.

An NxN photonic crossbar (PXBar) can be constructed with N N-to-1 MUX waveguides. In a PXBar, every output port is associated with a distinctive MUX waveguide, and all the input 4 ports can access to all the waveguides. In other words, each input port is connected to N different waveguides to send data to any output port.

Fig. 4. 4-to-1 photonic MUX 
 

(3) Photonic Broadcast Bus and Photonic Token Ring Bus
A photonic broadcast bus uses a waveguide and multiple couplers/splitters to connect the senders and receivers. Every time a sender wants to broadcast a signal, it will modulate the light into the data waveguide and the light will be split by splitters such that every receiver can receive/grab the signal from a connected waveguide.

The photonic token ring bus also uses a waveguide that has many senders and many receivers. Each wavelength of the waveguide can deliver one token signal. Unlike the broadcast bus in which every receiver receives the same signal from the sender, in the token ring bus only one receiver can capture the token signal released by the sender. To ensure each receiver has a chance to capture the token signal, the waveguide should form a ring shape so that the token can start from any point of the ring.

Part of our work can be found in [2][3].

Reference

[1] Najla Alfaraj, Junjie Zhang, Yang Xu, H. Jonathan Chao, "HOPE: Hotspot congestion control for Clos network on chip", in the Proceedings of 2011 Fifth ACM/IEEE International Symposium on Networks on Chip (NOCS), Pittsburg, May 2011.
[2] Y. H. Kao and H. J. Chao, "BLOCON: A Bufferless Photonic Clos Network-on-Chip Architectures", in the Proceedings of 2011 Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburg, May 2011
[3] Y. H. Kao, N. Alfaraj, M. Yang, and H. J. Chao, "Design of High-Radix Clos Network on Chip", in the Proceedings of 2010 ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 2010